1. Field of the Invention
This invention relates to a computer subsystem architecture, a programmable logic device, and a method that employs a programmable logic device integrated circuit functioning on a single substrate with a non-volatile memory integrated circuit to produce a high speed, high density volatile memory-based programmable logic device ("PLD") that will appear to the user as being non-volatile.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Programmable arrays or PLDs are commonly used to implement logic networks. PLDs are general-purpose digital components which are manufactured in an non-programmed state, and are later programmed to implement a desired logical function. A PLD is typically programmed by a sequence of electrical pulses which configure one or more arrays of programmable switching elements within the PLD. Examples of different types of PLDs include programmable read-only memories ("PROMs"), field programmable logic arrays ("FPLAs"), programmable array logic devices ("PALs), field programmable gate arrays ("FPGAs"), and complex programmable logic devices ("CPLDs").
The configuration of internal switches are programmed after the particular logic function of the PLD has been prepared and checked using a computer-aided design package appropriate for the PLD family used. As such, the PLD embodies a logic block containing an array of programmable switches. The switches can be permanently set or "programmed," or temporarily set depending on whether the PLD is considered a volatile memory-based PLD or a non-volatile memory-based PLD. For example, fuses, anti-fuses, or floating gates generally known in the EPROM technologies, can be used to establish non-volatile memory cells within the logic block. Conversely, volatile memory cells can be dynamically reset, programmed or maintained only when power exists to the PLD. Typical volatile memory cells include, for example, random access memory ("RAM") or static RAM ("SRAM").
Depending on the desired logic network, the logic block of a PLD can either be an array of volatile or non-volatile memory cells coupled to an AND array or an OR array to produce product terms or sum terms, respectively. The logic block or array architecture can thereby be classified as a product term array, a sum term array, or both. Also, the logic block of a PLD can be arranged as a programmable logic array ("PLA"), a programmable array logic ("PAL"), or a programmable array of gates known as programmable gate array ("PGA").
Resulting from the modem capability including an increasingly larger number of gates, multiple PLDs can be embodied upon a single monolithic substrate. The high-density PLDs may entail numerous interconnected logic blocks, generally described as complex PLDs, or CPLDs. While CPLDs differ somewhat from FPGAs, in that CPLDs have generally fixed, non-segmented routing (i.e., fixed propagation time). For purposes of the present application, CPLDs may include modem FPGAs. Additionally, a CPLD may be considered a highly integrated interconnection of multiple PLDs. The terms PLD, CPLD and FPGA may henceforth be used interchangeably and are deemed to have the same meaning. Moreover, logic blocks set forth in a PLD, CPLD or FPGA herein include product term arrays, sum terms arrays, look-up tables, or a combination of each.
FIG. 1 illustrates in more detail the various circuit elements of a CPLD 10. CPLD 10 includes multiple logic blocks 12 interconnected with a programmable interconnect matrix 14. The number of logic blocks 12 within a complex PLD ranges anywhere from two to beyond sixteen. Each logic block 12 is coupled to other logic blocks and an input/output macro cell 16 via the interconnect matrix 14. Communication to and from the integrated circuit PLD 10 takes place over pins 18 operably coupled to input/output cells 16.
FIG. 2 illustrates further details of an exemplary logic block 12. According to the example shown, logic block 12 can comprise a product term array 20, a product term allocator 22, and macro cells 24. Inputs to product term array 20 can arise from either the programmable interconnect matrix 14 or the input/output cell 16 (shown in FIG. 1). The product term allocator 22 receives the product term from array 20, and allocates or routes that product term to different macro cells 24 depending upon where they are needed. Product term allocator 22 may include an array of volatile or non-volatile memory cells. Macro cells 24 accepts the single output of the product term allocator, wherein the product term allocator 22 ORs the variable number of product terms arising from array 20. Depending on the architecture used, macro cells 24 can be configured as a flip flop, synchronous or asynchronous logic, inverting or non-inverting logic, or any other logic function. The output from macro cells 24 can be fed either to the programmable interconnect matrix or the input/output macro cell. Further details of logic block architecture and, specifically, items 20, 22, and 24 can be obtained in reference to Cypress Semiconductor Corp., part no. CY370 family, or FLASH370.TM..
FIG. 3 illustrates in further detail product term and sum term arrays 30 and 32, respectively. In particular, product term arrays are generally known as a matrix of input and output conductors programmable at the interconnection therebetween. The output conductors can be fed into an AND array 34 to encompass a product term array 30. Output from the product term array 30 can be fed into a sum term array, or an OR array 32, if desired. The sum term array is classified as such based on the output conductors feeding into OR gates 36.
The product term array 20, shown in FIG. 2, may be implemented as array 30 with AND gate outputs 34 shown in FIG. 3. Product term allocator 22, shown in FIG. 2, however can encompass the sum term array 32, shown in FIG. 3. It is important to note that the array of memory cells need not necessarily be a product array. Instead, the array can be a sum array or a combination of product and sum terms, depending on the desired degree of programmability. Regardless of the form taken, it is generally desired that the array be non-volatile. In order that the PLD not lose its programmed state when power is lost, each cross-point switch is preferably a fuse, anti-fuse, or EEPROM cell. More preferably, the matrix of memory cells can constitute a flash EEPROM. Flash EEPROMs are advantageous if fast erase and high density applications are desired. A flash EEPROM cell is generally a single transistor comprising a control gate dielectrically spaced above a floating gate. The floating gate receives programmed charge and maintains that charge over a relatively long period of time (e.g., approximately 10 years or longer).
Both the flash EEPROM single-transistor cell and the EEPROM cell in general have several disadvantages. First, the gate lengths of a control and/or floating gate are typically much greater than gate lengths of a conventional CMOS transistor. Secondly, the gate dielectric between the floating gate and the channel must be processed relatively thin in a select region in order to form a tunnel oxide necessary for Fowler-Nordheim tunneling. The processing sequence needed to fabricate an EEPROM cell is altogether different from the sequence used in forming a standard CMOS transistor. The non-volatile fabrication process (i.e., EEPROM, flash EPROM, PROM, etc.) typically lags the CMOS process by at least one generation. This results in slower operation speeds using non-volatile processes compared to the CMOS process.
While it is desirable to utilize the non-volatile aspects of EEPROM, it would be desirable not to employ EEPROM on the same monolithic substrate as an integrated circuit having higher density CMOS structures. Removing the EEPROM devices from the substrate having CMOS devices would beneficially reduce the overall size of the PLD and improve performance.